- 36 h for the core implementation
- C90 source language
- RISC-V target ISA
Takes pre-processed C90 source and emits RISC-V assembly. Handles functions and function calls with a correct calling convention, variables and scoping, the C data types, arithmetic and boolean operations, control flow, and the register allocation and stack-frame management underneath all of it.
The design decision that mattered was the internal instruction representation sitting between the parse tree and the emitted assembly. Get it wrong and every subsequent pass fights it. Lexer and parser feed into the code-generation passes across clean layer boundaries, so adding a language feature touches one layer rather than three.
Used STL containers throughout rather than hand-rolling, which turned into a practical education in the C++ memory model: ownership across a tree of nodes that outlive their creators is where the theory stops being theory.
Every feature landed with tests that compiled real C programs, ran the output and checked the results. The core came together in a 36-hour stretch, which is the sort of constraint that forces you to pick the right abstraction first time.